1. Field of the Invention
The present invention relates to an apparatus for converting a sampling frequency of a digital signal, and in particular, to an apparatus for carrying out sampling frequency conversion required in a decoding operation of a MUSE signal.
2. Description of the Related Art
In order to carry out various processings on information signals at a high speed and with a high precision, the information signals are generally converted into digital signals for processings. Image signals transmitting a large amount of information are also subjected to such conversion. The image signals are essentially analog signals, and thus are sampled at a certain sampling frequency for conversion into digital signals. As one type of information signal to be digitally processed, there is an image signal referred to as MUSE (multiple sub-Nyquist subsampling subencoding) signal. The MUSE signal is used in high definition television broadcast. The high definition television signal is transmitted through a communication satellite. One channel has a bandwidth of 27 MHz. A base band signal band width must be band-compressed into about 8 MHz. The signal thus band-compressed is referred to as MUSE signal.
FIGS. 11A-11E show a manner of band-compressing a luminance signal in the MUSE system. The MUSE system will be described below with reference to FIGS. 11A-11E. In FIG. 11A, an original image signal is sampled at a sampling frequency of 48.6 MHz and is converted into a digital signal. Thereafter, processings such as .gamma.-correction and matrix processing are carried out to generate a luminance signal Y. The luminance signal Y is sampled at a sampling frequency of 48.6 MHz. In FIG. 11A, a curve I indicates a relative value of spectrum strength.
In FIG. 11B, interfield offset sampling is performed on the luminance signal sampled at the sampling frequency of 48.6 MHz. The sampling frequency is 24.3 MHz. In this interfield offset sampling operation, the sampling is started at different timings every fields. As a result, high frequency component of the input signal is folded at the frequency of 12.15 MHz, as indicated by curve II in FIG. 11B.
Referring to FIG. 11C, after a low-pass filter removes a frequency component of 12.15 MHz or more, data is interpolated, and the sampling frequency is restored into 48.6 MHz.
Referring to FIG. 11D, the sampling frequency is converted from 48.6 MHz to 32.4 MHz.
In FIG. 11E, interframe offset sampling is carried out. In the interframe offset sampling, image data is subsampled while offsetting the position in each frame by one pixel position. Due to the interframe offset sampling, the sampling frequency goes to 16.2 MHz. The interframe offset sampling reduces the amount of data into 1/2 of that at the sampling frequency of 32.4 MHz.
Due to this interframe offset sampling, the high frequency band component of 8.1 MHz or more of the original signal is entirely contained as a folded component in the band lower than 8.1 MHz. In FIG. 11E, curve III indicates the interframe folded component. Curve II indicates the interfield folded component. The luminance signal of the sampling frequency of 16.2 MHz obtained by this interframe offset sample is multiplexed with a line sequential chrominance signal, which in turn has been processed in a similar manner, and is transmitted as an analog signal.
A principle of MUSE system can be summarized as follows. After conversion of a base band signal into a digital signal, subsampling of sampling points are uniformly performed. One sample is extracted from every four samples of image data for one picture (frame) to form one field. In this processing, the sampling positions are offset by one sample every fields (offset sampling). The positions of pixels are the same in every four fields.
FIG. 12 shows a sampling pattern of an image signal. In each scanning line, field numbers are superposed on pixel positions.
In a recovering operation, an image of one frame is produced from four fields. No problem is caused when a picture is still. This cannot be applied for a moving picture. Therefore, in the MUSE decoder for recovering MUSE signal, the signal processing is carried out in different manners for a motion area including a moving object and a still area not including a moving object.
More specifically, as shown in FIG. 12, the picture in the still area is recovered using the entire data of four fields (one frame) (entire data of first to fourth fields in FIG. 12). For this recovery, it is necessary to interpolate the data by precisely executing signal processing in a manner opposite to that of the interframe offset sampling and interfield offset sampling. If such processing were not executed, the folded component would appear as interference in the picture.
The picture in the motion area is recovered based on data of one field (e.g., data of only 1st field in FIG. 12). The horizontal resolution is approximately a half of that of the still area. In a visually displayed picture, edges blurs. The reason why the MUSE system employs this processing manner for the motion area is based on evaluation of perception that resolution of human eyes to a moving object is low.
FIG. 13 schematically shows a whole structure of a MUSE decoder. The MUSE decoder recovers image signals from band-compressed MUSE signals. In the MUSE decoder, the band-compressed MUSE signals are processed in different manners for the still and motion areas. For the still area, the signal is decoded from data of four fields by two processings, i.e., interframe interpolation and interfield interpolation. For the motion area, the signal is decoded from data of one field by interpolation.
In FIG. 13, the MUSE decoder includes a low-pass filter (LPF) 502 for band-limiting the MUSE signal, an A/D converter 504 for converting the output of low-pass filter 502 into a digital signal, and a non-linear processing circuit 506 for non-linearly processing the digital signal supplied from the A/D converter 504. The low-pass filter 502 has a cutoff frequency of 8.2 MHz, and passes the MUSE signal of a band of 8.1 MHz. The A/D converter 504 samples the analog signal sent from the low-pass filter 502 at the sampling frequency of 16.2 MHz and converts the same into the digital signal. The non-linear processing circuit 506 carries out processes such as reverse .gamma. correction and waveform equalizing process.
The MUSE decoder further includes an intrafield interpolating circuit 512 which receives the output of non-linear processing circuit 506 and performs intrafield interpolation, a motion area detecting circuit 508 which receives the output of non-linear processing circuit 506 and detects the motion area, an interframe interpolating circuit 510 which receives the output of non-linear processing circuit 506 and performs interframe interpolation, a sampling frequency converting circuit 514 which converts the sampling frequency of output of intrafield interpolating circuit 512, a sampling frequency converting circuit 518 which receives the output of interframe interpolating circuit 510 and converts the sampling frequency, and an interfield interpolating circuit 520 which receives the output of sampling frequency converting circuit 518 and performs interfield interpolation.
The interframe interpolating circuit 510, sampling frequency converting circuit 518 and interfield interpolating circuit 520 form a path for processing the signal for still area. The intrafield interpolating circuit 512 and sampling frequency converting circuit 514 form a path for processing the signal for motion area. Both the sampling frequency converting circuits 514 and 518 convert the sampling frequency of luminance signal from 32.4 MHz to 48.6 MHz, and convert the sampling frequency of chrominance signal from 32.4 MHz to 64.8 MHz. The motion area detecting circuit 508 detects a high band component (corresponding to a state of rapid motion) viewed on a time frequency base. The MUSE system performs the interframe offset sampling. In order to detect the motion area, therefore, differences of sampling values between the frames containing the same sampling points, i.e., between the second and fourth frames and between the first and third frames are obtained, respectively, and a difference between both the differences is combined. Thereby, the motion area for each frame can be detected. More specifically, a difference between the supplied MUSE signal and the signal delayed by two frames is obtained. The absolute value thereof is obtained, and is compared with the absolute value signal delayed by one frame to obtain a larger value, i.e., the maximum value to be output. This maximum value forms the motion area detecting signal.
The MUSE decoder further includes a multiplier circuit 516 which performs multiplication of the output of sampling frequency converting circuit 514 and the motion area detecting signal sent from the motion area detecting circuit 508, an inverter circuit 522 inverting the motion area detecting signal sent from the motion area detecting circuit 508, a multiplier circuit 524 for multiplying the output of interfield interpolating circuit 520 by the output of inverter circuit 522, an adder circuit 525 for performing addition of the multiplier circuits 516 and 524 for mixing the motion and still areas, a TCI decoder 526 performing a TCI decoding operation on the output of adder circuit 525, and an analog processing circuit 528 which performs required processing for producing R, G and B signals after converting the output of TCI decoder 526 into an analog signal.
The TCI decoder 526 converts the line sequential chrominance signals (in which (R-Y) signals and (B-Y) signals alternately appears) into signals appearing on respective original lines. The TCI decoder 526 also performs time-base correction by time-expanding the time-base compressed chrominance signal and luminance signal. The analog processing circuit 528 converts the output sent from the TCI decoder 526 into an analog signal, and then performs an inverse matrix operation to produce R, G and B signals. Then, brief descriptions will be successively made on operations for the intrafield interpolation, conversion of sampling frequency, interframe interpolation and interfield interpolation.
FIG. 14 shows distribution of sampling points when the intrafield sampling is performed. Distribution of the sampling data shown in FIG. 14 is given by the output of intrafield interpolating circuit 512 shown in FIG. 13. "Interpolation" is an operation by which data at points not sampled are approximately produced from data at sampled points. The intrafield interpolating circuit 512 corrects or interpolates data in the field based on the supplied data. More specifically, as shown in FIG. 14, data (indicated by "1" in FIG. 14) of the first field is processed in a certain manner to form interpolated data indicated by "1'" in FIG. 14. The sampling frequency of output of intrafield interpolating circuit equals 32.4 MHz. This equals an operation opposite to that shown in FIG. 11D.
FIG. 15 shows an output sample pattern of the interframe interpolating circuit 510. The interframe interpolation is a processing performed on an image in the still area. Image data which precedes by two fields is interpolated. Image data which precedes by one frame may be employed. Since the interframe offset sampling is carried out, the image data preceding by one frame exists at a position intermediate the sampling points of current frame. Owing to the interframe interpolation, image data of the sampling frequency of 32.4 MHz is obtained from the sample data of sampling frequency of 16.2 MHz.
Then, the image data of which sampling frequency was converted into 32.4 MHz by the intrafield interpolating circuit 512 and interframe interpolating circuit 510 is converted into the image data of sampling frequency of 48.6 MHz. The purpose of the conversion of sampling frequency is to perform the intrafield interpolation, and the reason thereof is that the original image data was sampled at the sampling frequency of 48.6 MHz.
FIG. 16 shows distribution of output sample data of the interfield interpolating circuit 520. The interfield interpolating circuit 520 interpolates image data of line of a preceding field for every one field. Since the sampling positions in the respective fields are different from each other, the image data of the preceding field is interpolated in the position in which the image data is not present. Thereby, image corresponding to the original still area can be obtained. Using the motion area detecting signal sent from the motion area detecting circuit 508, one of the output of intrafield interpolating circuit 512 and the output of interfield interpolating circuit 520 is selected to obtain image data corresponding to the motion area and still area.
The sampling frequency of 16.2 MHz can be converted relatively easily into the sampling frequency of 32.4 MHz. This can be achieved merely by the "interpolation" processing. For the conversion of sampling frequency of 32.4 MHz into the image data of sampling frequency of 48.6 MHz, two image data must correspond to three image data.
Specifically, as shown in FIG. 17, owing to 32.4 MHz:48.6 MHz=2:3, two image data P1 and P2 at the sampling frequency of 32.4 MHz correspond to three image data Q1, Q2 and Q3 at the sampling frequency of 48.6 MHz. A structure for performing this frequency conversion will be described below.
FIG. 18 shows a structure of a sampling frequency converting circuit in the prior art. In FIG. 18, the sampling frequency converting circuit includes a two-phase parallel converting circuit 600 which successively receives input data train and supplies in parallel the data train in odd places (odd generation data train) and the data train in even places (even generation data train), a table processing circuit 610 which receives parallel outputs from the two-phase parallel converting circuit 600 and performs a predetermined arithmetic operation for outputting the result, a parallel processing circuit 620 which receives the output of table processing circuit 610 and performs a predetermined arithmetic operation on the same for outputting in parallel three kinds of data, and a switching circuit 630 which successively and selectively passes the outputs of parallel processing circuit 620 in a predetermined order.
The two-phase parallel converting circuit 600 includes a D-type flip-flop 602 strobing, latching and outputting the data, which is supplied to an input D in synchronization with a clock signal .phi.1 applied to a clock input CK, a D-type flip-flop 604 which strobes, latches and outputs the output of D-type flip-flop 602 received at its input D in response to a clock signal .phi.2 applied to the clock input CK, and a D-type flip-flop 606 which strobes, latches and outputs data applied to the input D in response to the clock signal .phi.2 applied to the clock input CK. The clock signal .phi.1 has a frequency of 32.4 MHz, and the clock signal .phi.2 has a frequency of 16.2 MHz.
The table processing circuit 610 includes two table ROMs (read-only memories) 612 and 614 which have stored results of multiplication and outputs the results of multiplication of input data by predetermined coefficients using applied data as address signals, respectively. The table ROM 612 receives the output of D-type flip-flop 604 as an address signal, and outputs in parallel the results of multiplication of this data by coefficients .alpha.1, .alpha.3 and .alpha.5. The table ROM 614 receives the output of D-type flip-flop 606 as an address, and outputs in parallel the results of multiplication of this data by coefficients .alpha.0, .alpha.2, .alpha.4 and .alpha.6.
The parallel processing circuit 620 includes a timing control circuit 622 which receives in parallel the output data from the table processing circuit 610 and controls or adjusts the timing for performing a predetermined operation, and an processing circuit 624 which performs a predetermined operation on the data controlled by the timing control circuit 622. The timing control circuit 622 includes a delay circuit and others, and controls a transmission time of the input data so as to transmit data combined in a predetermined manner to the processing circuit. The processing circuit 624 performs a predetermined operation on the applied data, of which content will be described later, and outputs three kinds of data in parallel.
The switching circuit 630 includes a 3-input and 1-output switching circuit, which receives the outputs of parallel processing circuit 620 in parallel and sequentially switches its inputs in accordance with a clock signal .phi.3 for outputting. The clock signal .phi.3 has a frequency of 48.6 MHz. Then, an operation of this sampling frequency converting circuit shown in FIG. 18 will be described below also with reference to FIG. 19. FIGS. 19A-19E show patterns of sampling data at portions A, B, C, D and E in the sampling frequency converting circuit shown in FIG. 18.
A shown in FIG. 19A, the two-phase converting circuit 600 sequentially receives a data train X1, X2, . . . sampled at the sampling frequency of 32.4 MHz. The D-type flip-flop 602 latches and output this input data in response to the clock signal .phi.1. The D-type flip-flop 602 serves as a delay circuit which delays the applied data by one clock cycle of the clock signal .phi.1 and outputting the same. Therefore, the D-type flip-flop 604 receives input data Xj (where j is a natural number) which is delayed by one clock with respect to data received by the D-type flip-flop 606.
Each of the D-type flip-flops 604 and 606 latches the applied data in accordance with the clock signal .phi.2 of frequency of 16.2 MHz and outputting the same. Therefore, the output of each of the D-type flip-flops 604 and 606 equals sampling data formed by alternately subsampling the input data. Data delayed by one clock cycle is transmitted to the D-type flip-flop 604. Therefore, the D-type flip-flop 604 outputs the even-generation data train formed of data X2i bearing even numbers. The D-type flip-flop 606 outputs the data train of odd-generation data X2i+1 bearing odd numbers. Since the odd-generation data X2i+1 and even-generation data X2i are output in response to the clock signal .phi.2, they are output at the same timing.
The table processing circuit 610 outputs in parallel the results of multiplication of the odd-generation data X2i by the coefficients .alpha.1, .alpha.3 and .alpha.5, and also outputs in parallel the results of multiplication of the even-generation data X2i+1 by the coefficients of .alpha.0, .alpha.2, .alpha.4 and .alpha.6. The table processing circuit 610 outputs the sampling data train at the sampling frequency of 16.2 MHz.
The parallel processing circuit 620 performs a predetermined operation on the applied data, and outputs in parallel three data Y3i, Y3i+1 and Y3i+2 (where i is an integer such as 0, 1, . . . ). More specifically, the processing circuit 624 outputs data Y1, Y2 and Y3 obtained from the data X1, X2, . . . X5 produced by the timing control circuit 622 in accordance with the following formulas (1). EQU Y1=.alpha.4.multidot.X1+.alpha.1.multidot.X2+.alpha.3.multidot.X3+.alpha.5. multidot.X4 EQU Y2=.alpha.6.multidot.X1+.alpha.3.multidot.X2+.alpha.0.multidot.X3+.alpha.3. multidot.X4+.alpha.6.multidot.X5 EQU Y3=.alpha.5.multidot.X2+.alpha.2.multidot.X3+.alpha.1.multidot.X4+.alpha.4. multidot.X5 (1)
The parallel processing circuit 620 outputs the data at the sampling frequency of 16.2 MHz.
The switching circuit 630 successively outputs the data Y3i, Y3+1 and Y3i+2 supplied from the parallel processing circuit 620 in response to the clock signal .phi.3. Thereby, the switching circuit 630 outputs the sampling data train Y1, Y2, Y3, . . . having the sampling frequency of 48.6 MHz.
As described above, three data Y3i, Y3i+1 and Y3i+2 are produced using the two data, i.e., odd-generation data X2i and even-generation data X2i+1, so that the sampling frequency is increased 3/2 times.
Conversion of the sampling frequency of digital signal conventionally requires dedicated sampling frequency converter formed of a digital circuit which has a required processing function. If the dedicated sampling frequency converter is to be used, it is necessary to prepare a table processing circuit, to control input/output timings of data between any circuits and to optimize structures of timing control circuit and processing circuit for simplifying a structure of parallel processing circuit. Although the sampling frequency converter formed of the dedicated circuit has an advantage that the intended function can be ensured, it disadvantageously requires a long time for designing the same.
Also, in order to change a specification of frequency conversion, i.e., contents of calculation (values of coefficients .alpha.0-.alpha.6 and contents of operation performed by the parallel processing circuit), it is necessary to utilize another dedicated digital circuits which are designed for the respective circuit portions. Therefore, the sampling frequency converter formed of the dedicated circuits cannot flexibly accommodate the change of specification.
In the MUSE decoders of which specification has been generally decided, particular change of its structure is not required for a purpose other than improvement of its circuitry after an optimized sampling frequency converter is once obtained. However, apparatuses referred to as simple type MUSE decoders are currently used. The simple type MUSE decoder performs the decoding of which processing contents are simplified in order to receive and recover high definition television signals by an inexpensive receiver. For this purpose, it is necessary to change the contents of operation required for the conversion of sampling frequency in accordance with the contents of simplified decoding processing. In the case where the sampling frequency converter formed of dedicated digital circuits is used, therefore, new design of circuits is required, and thus the change of specification (contents of operation) cannot be flexibly accommodate.
Also, a similar problem is generally caused in fields, other than the MUSE decoder, in which band-compressed signals are interpolated to recover original signals, because conversion of sampling frequencies is required in such fields.